1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. In particular, the present invention relates to a CMOS (complementary insulated gate) output buffer circuit, which is used for a semiconductor memory such as a DRAM.
2. Description of the Related Art
In general, when simultaneously outputting a multi-bit signal from a semiconductor integrated circuit (hereinafter, referred to as an IC or LSI) including a plurality of output buffer circuits, consideration must be given to the influence of switching noise generated when output buffer circuits switch simultaneously.
FIG. 4 shows a conventional IC package model including a plurality of CMOS output buffer circuits 40. FIG. 5 shows waveforms {circle around (1)} and {circle around (2)} of switching noise generated when a plurality of output buffer circuits switch simultaneously in the fall of an input signal IN.
In the output buffer circuit 40, p-channel and N-channel buffers connected in series between a power supply node (VDD node) and a ground node are complementarily turned on by the input signal IN. In FIG. 4, L is parasitic inductance of external wiring of an IC package, and CL is load capacitance.
When a plurality of output buffer circuits 40 simultaneously switch, the corresponding capacitive load connected to a plurality of output terminals is charged and discharged. Thus, rapid current variations occur in the transient state when the output buffer circuit 40 makes the switching operation.
This is a factor of generating the following switching noise. More specifically, the switching noise (waveform {circle around (2)}) is generated in the output signal resulting from the foregoing parasitic inductance L. The switching noise (waveform {circle around (1)}) is generated in the potential of the ground terminal. The higher the drive capability of the output buffer circuit 40 is, the greater the switching noise becomes. As a result, a remarkable influence is had on the inside and outside of the IC. In order to reduce the switching noise, a slew rate control (SRC) circuit is employed.
FIG. 6 shows an equivalent circuit diagram of a typical output buffer circuit formed using the SRC circuit when the output buffer circuit 40 of FIG. 4 requires high drive capability.
The SRC circuit comprises a CMOS pre-buffer 50 receiving an input signal from a first-stage circuit and an output buffer 60 driven by the output signal of the pre-buffer 50. The output buffer 60 comprises P-channel and N-channel buffers 60a and 60b, which are connected between a VDD node and a ground node. The P-channel buffer 60a is composed of a plurality of PMOS transistors PT, which are connected in parallel, and individually have a gate connected to a polysilicon gate interconnection (wiring) 61a. The N-channel buffer 60b is composed of a plurality of NMOS transistors NT, which are connected in parallel, and individually have a gate connected to a polysilicon gate interconnection 61b. In this case, CR delay effect of gate capacitance C of multi-stage PMOS and NMOS transistors PT and NT and polysilicon resistance R parasitic to polysilicon gate interconnections 61a and 61b is used. Using the CR delay effect, multi-stage PMOS and NMOS transistors PT and NT of the output buffer 60 are stepwise turned on by the output of the pre-buffer 50, and thereby, current variations are softened.
However, the SRC circuit has the conflicting relationship between switching noise and propagation delay time as described below.
FIG. 7 shows an equivalent circuit of the SRC circuit shown in FIG. 6 to which propagation path nodes of the input signal IN are added. FIG. 8 is a view to explain the delay propagation operation with respect to multi-stage PMOS and NMOS transistors PT and NT of the output buffer when the input signal IN rises.
The SRC circuit shown in FIG. 7 intentionally delays potential propagation in the termination node of input nodes a, b, c, d and e corresponding to multi-stage PMOS and NMOS transistors PT and NT of the output buffer 60. Therefore, when the switching operation is made, a state in which P-channel and N-channel buffers 60a and 60b simultaneously turned on continues for a long time. In addition, when switching rush current increases, the carrying period simultaneously becomes long. As a result, the switching operation time of the SRC circuit becomes slow; for this reason, this remarkably influences propagation delay time.
FIG. 9 is an equivalent circuit diagram showing a modification example of the SRC circuit shown in FIG. 7. FIG. 10 is a waveform chart to explain the operation when the input signal IN falls.
The SRC shown in FIG. 9 has the circuit connection described below. Multi-stage PMOS and NMOS transistors PT and NT of the output buffer 60 are divided into a plurality of unit groups. In each group, input signal propagation delay time becomes equal, and potential propagation is delayed in the termination node, that is, input nodes a and e of each group.
In view of the propagation delay time of the SRC circuit, the SRC circuit reduces it to some degree; however, the effect of reducing switching noise is not so expected.
JPN. PAT. APPLN. KOKAI Publication No. 2001-244802 discloses the following buffer circuit. The buffer circuit includes two switching elements, two auxiliary switching elements and drive changeover (switching) control section. The two switching elements are connected in series to a power source, exclusively make on/off changeover by an input signal, and output the output signals from a common connection node. The foregoing two auxiliary switching elements are connected in parallel correspondingly to two switching elements. The drive changeover control section outputs a drive auxiliary control signal for turning on the auxiliary switching elements by predetermined time in accordance with a level change of the input signal.
As described above, the CMOS output buffer circuit simultaneously outputs a plurality of bit signal in a conventional LSI. The CMOS output buffer circuit is greatly influenced by switching noise. If the SRC circuit is used in order to reduce the switching noise, switching time becomes slow. As a result, there is a problem of influencing the propagation delay time of the LSI.